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ISCA
2005
IEEE

Opportunistic Transient-Fault Detection

14 years 5 months ago
Opportunistic Transient-Fault Detection
CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage while incurring significant performance degradation. However, most commodity systems do not need or provide perfect coverage. A recent paper explores this leniency to reduce the soft-error rate of the issue queue during L2 misses while incurring minimal performance degradation. Whereas the previous paper reduces soft-error rate without using any redundancy, we target better coverage while incurring similarly-minimal performance degradation by opportunistically using redundancy. We propose two semi-complementary techniques, called partial explicit redundancy (PER) and implicit redundancy through reuse (IRTR), to explore the trade-off between soft-error rate and performance. PER opportunistically exploits low-ILP phases and L2 misses to introduce explicit redundancy with minimal performance degradation. Becaus...
Mohamed A. Gomaa, T. N. Vijaykumar
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCA
Authors Mohamed A. Gomaa, T. N. Vijaykumar
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