Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders

— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes and propose an encoder and decoder architecture that is implementable as an ASIC. We report upon a realization of this new architecture capable of an information throughput of 430 Mbps and 164 Mbps for the encoder and decoder, respectively. We discuss a top-level chip specification and then extend ideas to parallelize the design.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon
• Keywords: Block-oriented Counterparts, Decoder Architecture, ISCAS 2005, Parity-check Convolutional Codes