Fast configurable-cache tuning with a unified second-level cache

Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. We instead use a commercially-common unified second level, a seemingly minor difference that actually expands the configuration space from 500 to about 20,000. We develop additive way tuning for tuning a cache subsystem with this large space, yielding 62% energy savings and 35% performance improvements over a non-configurable cache, greatly outperforming an extension of a previous method. Categories and Subject Descriptors B.3.2 [Hardware]: Memory Structures: Design Styles – cache memories. General Terms Design. Keywords Configurable cache, cache hierarchy, cache exploration, cache optimization, low power, low energy, architecture tuning, embedded systems.

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
• Keywords: Cache Subsystem, Configurable Cache, Configurable Cache Subsystem, ISLPED 2005