Power and Area Optimization for Multiple Restricted Multiplication

This paper presents a design and optimization technique for the Multiple Restricted Multiplication problem [1]. This refers to a situation where a single variable is multiplied by several coefficients which, while not constant, are drawn from a finite set of constants that change with time. The approach exploits dedicated registers in FPGA architecture for further time-step based optimization over previous approaches [1, 2]. It is also combined with an effective technique, based on high-level power modelling, for power optimization. The problem is formulated into an integer linear program for finding solutions to the minimum-costs. The new approach results up to 22% area saving compared to the optimal non-register approach in [1], and 80% of all results also show 21%-48% power savings.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
• Keywords: FPL 2005, Multiple Restricted Multiplication, Optimization Technique, Time-step Based Optimization