An approach for reducing dynamic power consumption in synchronous sequential digital designs

— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address this problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and voltage scaling to address this NP-hard problem cannot in general be done in polynomial run-time. In this paper, we propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Experimental results on known benchmarks have shown that the proposed approach can reduce dynamic power consumptio...

• Type: Conference
• Year: 2004
• Where: ASPDAC
• Authors: Noureddine Chabini, Wayne Wolf
• Keywords: ASPDAC 2004, Dynamic Power Consumption, Supply Voltage, Voltage Scaling