A small-area high-performance 512-point 2-dimensional FFT single-chip processor

: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 x 2.8 mm2 with CMOS 0.35µm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1dimensonal FFT in 23.2 µsec and a 2-dimensional one in only 23.8 msec at 133MHz operation.

• Type: Conference
• Year: 2004
• Where: ASPDAC
• Authors: Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi
• Keywords: 512-point Fft Processor, ASPDAC 2004, FFT Processor, FFT Processor Core