Automatic Creation of Reconfigurable PALs/PLAs for SoC

Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurability, or even be used for post -fabrication modifications. Also, by catering the logic to the SoC domain, additional area/delay/power gains can be achieved over current, more general reconfigurable fabrics. This paper presents tools that automate the creation of domain specific PLAs and PALs for SoC, including an Architecture Generator for making optimized arrays and a Layout Generator for creating efficient layouts. By intelligently mapping netlists to PLA and PAL arrays, we can reduce 60%-70% of the programmable connections in the array, creating delay gains of 15%-30% over unoptimized arrays.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Mark Holland, Scott Hauck
• Keywords: Additional Area/delay/power Gains, Domain Specific Plas, FPL 2004, Many System-on-a-Chip Devices