Energy Aware Register File Implementation through Instruction Predecode

The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger devices to feed multiple data paths and to store global variables. However, low power techniques are not able to appreciably reduce power consumption in this device without a time penalty. This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty. The simplicity of the approach makes it an effective low-power technique for embedded processors.

• Type: Conference
• Year: 2003
• Where: ASAP
• Authors: José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez
• Keywords: ASAP 2003, Distributed And Parallel Computing, Low Power, Low Power Techniques, Register file