Hardware Synthesis for Multi-Dimensional Time

This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it also implies the use of memories in the architecture. The paper explains how to obtain compatible allocation and memory functions for vlsi (or simd-like code) generation. It also presents an original mechanism for controlling a vlsi architecture which has a multi-dimensional schedule. A structural vhdl code has been derived and synthesized (for implementation on fpga platform) using these systematic design principles. These results are preliminary steps to the possibility of a systematic hardware synthesis for multi-dimensional time.

• Type: Conference
• Year: 2003
• Where: ASAP
• Authors: Anne-Claire Guillou, Patrice Quinton, Tanguy Risset
• Keywords: ASAP 2003, Distributed And Parallel Computing, Multi-dimensional, Multi-dimensional Scheduling Enables, Multi-dimensional Time