BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability

A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of symmetric functions. Only one additional input and one inverter are needed to achieve 100% Path Delay Fault (PDF) testability. The size of the circuit is guaranteed to be at most quadratic in the number of inputs. The test vectors for any PDF can be generated in linear time. Experimental results underline the efficiency of the approach. In contrast to previous approaches, the technique can also be applied to multi-output functions.

• Type: Conference
• Year: 2003
• Where: ATS
• Authors: Junhao Shi, Görschwin Fey, Rolf Drechsler
• Keywords: ATS 2003, Delay Fault Testability, Hardware, Path Delay Fault, Symmetric Boolean Functions