Using Symbolic Simulation for Bounded Property Checking

Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. In this paper we describe a new technique of property checking using symbolic simulation which can be applied to larger designs. This technique seamlessly integrate formal verification and standard simulation. The proposed method is a formal verification technique which checks symbolically a given LTL specification against the Hardware Design. Our experimental results show a run time gain over standard symbolic model checking and SAT-based bounded model checking for certain classes of circuits and properties.

• Type: Conference
• Year: 2003
• Where: FDL
• Authors: Jürgen Ruf, Prakash Mohan Peranandam, Thomas Kropf, Wolfgang Rosenstiel
• Keywords: FDL 2003, Formal Verification, Formal Verification Technique, Model Checking