Sciweavers

FMSD
2010
118views more  FMSD 2010»
13 years 10 months ago
On simulation-based probabilistic model checking of mixed-analog circuits
In this paper, we consider verifying properties of mixed-signal circuits, i.e., circuits for which there is an interaction between analog (continuous) and digital (discrete) values...
Edmund M. Clarke, Alexandre Donzé, Axel Leg...
CAV
2001
Springer
121views Hardware» more  CAV 2001»
14 years 4 months ago
A Practical Approach to Coverage in Model Checking
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
Hana Chockler, Orna Kupferman, Robert P. Kurshan, ...
FDL
2003
IEEE
14 years 4 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
TPHOL
2005
IEEE
14 years 5 months ago
On the Correctness of Operating System Kernels
The Verisoft project aims at the pervasive formal verification of entire computer systems. In particular, the seamless verification of the academic system is attempted. This syst...
Mauro Gargano, Mark A. Hillebrand, Dirk Leinenbach...
MTV
2005
IEEE
100views Hardware» more  MTV 2005»
14 years 5 months ago
A Study of Architecture Description Languages from a Model-based Perspective
Abstract— Owing to the recent trend of using applicationspecific instruction-set processors (ASIP), many Architecture Description Languages (ADLs) have been created. They specif...
Wei Qin, Sharad Malik
TAP
2007
Springer
92views Hardware» more  TAP 2007»
14 years 5 months ago
Generating Unit Tests from Formal Proofs
We present a new automatic test generation method for JAVA CARD based on attempts at formal verification of the implementation under test (IUT). Self-contained unit tests in JUnit...
Christian Engel, Reiner Hähnle
SAFECOMP
2007
Springer
14 years 5 months ago
Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts
With the rapid progress in science and technology, we find ubiquitous use of safety-critical systems in avionics, consumer electronics, and medical instruments. In such systems, u...
Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen
HVC
2007
Springer
103views Hardware» more  HVC 2007»
14 years 5 months ago
Verifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
Ales Smrcka, Tomás Vojnar
MTV
2007
IEEE
166views Hardware» more  MTV 2007»
14 years 5 months ago
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...
Scott Little, Alper Sen, Chris J. Myers
FDL
2007
IEEE
14 years 5 months ago
A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set
Abstract—Property-based synthesis has become a more prominent topic during the last years, being used in multiple areas like e.g. formal verification and design automation. We w...
Martin Schickel, Martin Oberkönig, Martin Sch...