Buffer sizing for minimum energy-delay product by using an approximating polynomial

This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper describes a sizing method for tapered buffer chains. It is shown that the first-order sizing behavior, which considers only the capacitive energy dissipation, can be improved by considering the short-circuit dissipation as well, and that the second-order polynomial expressions for short-circuit energy improves the accuracy over linear expressions. These results are used to derive sizing rules for buffered chains, which optimize the overall energy-delay product. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – VLSI (very large scale integration), advanced technologies. General Terms Performance, Design. Keywords Buffer sizing, Short circuit energy, polynomial.

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
• Keywords: Circuit Energy Dissipation, Energy Dissipation, GLVLSI 2003, Short Circuit Energy, VLSI