Abstract--In this paper, we propose a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the ...
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
In the context of the RESUME-project a scalable wavelet-based video decoder was built to demonstrate the benefits of reconfigurable hardware for scalable applications. Scalable v...
Harald Devos, Hendrik Eeckhaut, Mark Christiaens, ...
Energy efficiency has become a critical concern in designing high speed packet classification engines for next generation routers. Although TCAM-based solutions can provide high th...
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run tim...
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
This paper describes the system design of a lowpower wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties...
Anantha Chandrakasan, Abram P. Dancy, James Goodma...
In this paper, we obtain the lower bounds on total energy dissipation of deep submicron (DSM) VLSI circuits via an informationtheoretic framework. This framework enables the deriv...
Although division is less frequent than addition and multiplication, because of its longer latency it dissipates a substantial part of the energy in floating-point units. In this ...
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...