Miss Rate Prediction across All Program Inputs

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets. This paper uses our recently published locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts the miss rate for arbitrary data input set sizes. This model also identifies critical data input sizes where cache behavior exhibits marked changes. Experiments show this technique is within 2% of the hit rate for set associative caches on a set of integer and floating-point programs.

• Type: Conference
• Year: 2003
• Where: IEEEPACT
• Authors: Yutao Zhong, Steve Dropsho, Chen Ding
• Keywords: Cache Behavior, Cache Performance, Data Input Set, Hardware, IEEEPACT 2003