Deformations of IC Structure in Test and Yield Learning

This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Traditional notions of a spot defect and local and global process variations are analyzed and their shortcomings are exposed. A detailed taxonomy of process-induced deformations of DSM IC structures, enabling modeling and characterization of IC malfunctions, is proposed. The blueprint of a roadmap enabling such a characterization is suggested.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
• Keywords: Characterization, Global Process Variations, Hardware, IC Malfunctions, ITC 2003