LLVA: A Low-level Virtual Instruction Set Architecture

A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examples such as Crusoe and DAISY, however, have used existing hardware instruction sets as virtual ISAs, which complicates translation and optimization. In fact, there has been little research on specific designs for a virtual ISA for processors. This paper proposes a novel virtual ISA (LLVA) and a translation strategy for implementing it on arbitrary hardware. The instruction set is typed, uses an infinite virtual register set in Static Single Assignment form, and provides explicit control-flow and dataflow information, and yet uses low-level operations closely matched to traditional hardware. It includes novel mechanisms to allow more flexible optimization of native code, including a flexible exception model and minor constraints on self-modifying code. We propose a translation strategy that enables offl...

• Type: Conference
• Year: 2003
• Where: MICRO
• Authors: Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke
• Keywords: Hardware, Hardware Instruction Sets, Instruction Sets, MICRO 2003, Virtual Isa