A low-power VLSI architecture for turbo decoding

Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of blockinterleaved computation followed by folding, retiming and voltage scaling. Block-interleaved Computation can be applied to any data processing unit that operates on data

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
• Keywords: Data Processing Unit, ISLPED 2003, Low-power Architecture, Turbo Decodings