PLDI
1995
ACM
14 years 3 months ago
1995
ACM
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
ICS
1999
Tsinghua U.
14 years 3 months ago
1999
Tsinghua U.
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
SIGMETRICS
2003
ACM
14 years 4 months ago
2003
ACM
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
DAC
1999
ACM
15 years 16 days ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...