Laura: Leiden Architecture Research and Exploration Tool

At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto reconfigurable platforms. In this chain, first the Matlab code is converted automatically to executable Kahn Process Network (KPN) specification. Then a tool called Laura accepts this specification and transforms the specification into design implementations described as synthesizable VHDL. In this paper, we present our methodology implemented in the Laura tool, to automatically convert KPNs to synthesizable VHDL code targeted for mapping onto FPGA-based platforms. With the help of Laura, a designer is able to either fast prototype signal processing and multimedia applications directly in hardware or to extract very fast valuable low-level quantitative implementation data such as performance in terms of clock cycles, time delays and silicon area.

• Type: Conference
• Year: 2003
• Where: FPL
• Authors: Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere
• Keywords: FPL 2003, Synthesizable Vhdl, Synthesizable Vhdl Code, Tool Called Laura