Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the configurable logic, it can execute common genetic operators like crossover and mutation with a targeted data throughput of 420 MByte/s. Together with the microprocessor core, a complex evolutionary algorithm can be developed in software, but is processed at the speed of dedicated hardware.

• Type: Conference
• Year: 2003
• Where: ICES
• Authors: Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Meier, Johannes Schemmel, Felix Schürmann
• Keywords: Coprocessor Architecture, ICES 2003, Integrated Microprocessor Core, Microprocessor Core