Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

28

DATE
2010
IEEE

favoriteEmaildiscussreport

165views Hardware» more DATE 2010»

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

14 years 4 months ago

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Download www.date-conference.com

Pramod Subramanyan, Virendra Singh, Kewal K. Saluj

Real-time Traffic

DATE 2010 | Hardware |

claim paper

Related Content

» Energyefficient redundant execution for chip multiprocessors

» Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Ar...

» A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

» Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

» TransientFault Recovery for Chip Multiprocessors

» Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherenc...

» Tolerating Transient Faults through an Instruction Reissue Mechanism

» Transparent dynamic binding with faulttolerant cache coherence protocol for chip multiproc...

» Rescue A Microarchitecture for Testability and Defect Tolerance

Post Info
More Details (n/a)

Added	10 Jul 2010
Updated	10 Jul 2010
Type	Conference
Year	2010
Where	DATE
Authors	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson

Comments (0)