Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STTMRAM)—a CMOS-compatible...

• Type: Conference
• Year: 2010
• Where: ISCA
• Authors: Xiaochen Guo, Engin Ipek, Tolga Soyata
• Keywords: Dynamic Power, Hardware, ISCA 2010, MOSFET Scaling Theory, Power Wall