Hardware/Software Trade-Offs for Advanced 3G Channel Coding

Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s systems. Numerous existing and emerging standards require flexible implementations (”software radio”). Thus efficient implementations of the performance-critical parts as Turbo decoding on programmable architectures are of great interest. Besides high-performance DSPs, application-customized RISC cores offer the required performance while still maintaining the aspired flexibility. This paper presents for the first time Turbo decoder implementations on customized RISC cores and compares the results with implementations on state-of-the-art VLIW DSPs. The results of our studies show that the Log-MAP performance is about 50 % higher than on an ST120, a current VLIW architecture.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch
• Keywords: DATE 2002, Hardware, Risc Cores, State-of-the-art Vliw Dsps, Turbo Decoder Implementations