A Video Compression Case Study on a Reconfigurable VLIW Architecture

In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preliminary results on the motion estimation stage in an MPEG4 video encoder are presented. With the RFU modeled at functional level and under realistic assumptions on execution latency, technology scaling and reconfiguration penalty, we explore different RFU instructions at fine-grain (instruction-level) and coarsegrain (loop-level) granularity to speedup the application execution. The memory bandwidth bottleneck, typical for streaming applications, is alleviated through the combined adoption of custom prefetch pattern instructions and an extent of local memory. Performance evaluations indicate up to 8x improvement, with looplevel optimizations is achieved under various architectural assumptions.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Davide Rizzo, Osvaldo Colavin
• Keywords: DATE 2002, Hardware, Memory Bandwidth Bottleneck, Motion Estimation Stage, Reconfigurable Functional Unit