Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models

The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, at least for the performance critical parts of the application. The highly encoded instruction sets simply lack the orthogonal structure present in e.g. VLIW processors, that allows efficient compilation. This lack of efficient compilation tools has also severely hampered the design space exploration of code-size efficient instruction sets, and correspondingly, their tuning to the application domain. In [13] a practical method is demonstrated to model a broad class of highly encoded instruction sets in terms of virtual resources easily interpreted by classic resource constrained schedulers (such as the popular list-scheduling algorithm), thereby allowing efficient compilation with well understood compilation tools. In this paper we will demonstrate the suitability of this model to also enable instruction ...

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Qin Zhao, Bart Mesman, Twan Basten
• Keywords: Compilation Tools, DATE 2002, Efficient Compilation, Hardware, Instruction Set