An FPGA Implementation of Triangle Mesh Decompression

This paper presents an FPGA-based design and implementation of a three dimensional (3D) triangle mesh decompressor. Triangle mesh is the dominant representation of 3D geometric models. The prototype decompressor is based on a simple and highly efficient triangle mesh compression algorithm, called BFT mesh encoding [10, 11]. To the best of our knowledge, this is the first hardware implementation of triangle mesh decompression. The decompressor can be added at the front-end of a 3D graphics card sitting on the PCI/AGP bus. It can reduce the bandwidth requirement on the bus between the host and the graphics card by up to 80% compared to standard triangle mesh representations. Other mesh decompression algorithms with comparable compression efficiency to BFT mesh encoding are too complex to be implemented in hardware.

• Type: Conference
• Year: 2002
• Where: FCCM
• Authors: Tulika Mitra, Tzi-cker Chiueh
• Keywords: BFT Mesh, FCCM 2002, Triangle Mesh, Triangle Mesh Decompressor, VLSI