Modeling Assembly Instruction Timing in Superscalar Architectures

This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provides a methodology and a toolset to perform data analysis and model tuning. The methodology also provides a framework for building new trace simulators for generic architectures. The results obtained show a good accuracy paired with a satisfactory computational efficiency. Categories and Subject Descriptors B.8.2 [Hardware]: Performance and Reliability—Performance Analysis and Design Aids; C.4 [Computer Systems Organization]: Performance of Systems—Modeling Techniques; I.6.5 [Computing Methodologies]: Simulation and Modeling—Model Development General Terms Languages, Performance Keywords Assembly-level analysis, Performance estimation, superscalar architectures

• Type: Conference
• Year: 2002
• Where: ISSS
• Authors: William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame
• Keywords: Hardware, ISSS 2002, Rigorous Mathematical Model, Satisfactory Computational Efficiency, Superscalar Architectures