Write activity reduction on flash main memory via smart victim cache

Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. There are two challenges in applying flash memory as main memory. First, the write operations are much slower than read operations. Second, the lifetime of flash memory depends on the number of the write/erase operations. In this paper, we introduce a smart victim cache architecture to reduce the write activities by exploring the coarse grain accessing character of NAND flash memory. Experimental results show that the proposed approaches can reduce write activities on flash main memory by 65.38% on average compared to traditional architecture. Categories and Subject Descriptors:B.3.2[Memory Structures]: Design Styles–Cache memories, Primary memory General Term:Design, Performance, Experimentation

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Xuehai Zhou, Edwin Hsing-Mean Sha
• Keywords: GLVLSI 2010, Main Memory, Main Memory Replacement, VLSI, flash Memory