Graphene tunneling FET and its applications in low-power circuit design

Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for large scale processing and fabrication. This paper combines atomistic quantum transport modeling with circuit simulation to explore GNR TFET circuits for low-power applications. A quantitative study of the effects of variations on the performance and reliability of GNR TFET circuits is also presented. Simulation results indicate that GNR TFET circuits are extremely competitive in performance in comparison to conventional CMOS circuits at comparable operating points, with static power consumption that is lower by 8–9 orders of magnitude. It is also observed that GNR TFET circuits are susceptible to parameter variations, motivating engineering and design challenges to be addressed by the device and CAD communities. Categories and Subject Descriptors: B.7.1 [Integrated circuits]: Types and Design Styles—Advan...

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram
• Keywords: GLVLSI 2010, Gnr Tfet, GNR TFET Circuits, Low-power Applications, VLSI