ARPIA: A High-Level Evolutionary Test Signal Generator

The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones. 1 Background In recent years the application specific integrated circuit (ASIC) design flow experienced radical changes. Deep sub-m...

• Type: Conference
• Year: 2001
• Where: EVOW
• Authors: Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
• Keywords: Artificial Intelligence, Design Flows, EVOW 2001, Fault Model, Integrated Circuit