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ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
12 years 3 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim

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tyusemanEngineer
MIPT
tyuseman
But it ain’t about how hard you hit... it’s about how hard you can get hit, and keep moving forward. It’s how much you can take, and keep moving forward. That’s how winning...
ICCAD
2009
IEEE
144views Hardware» more  ICCAD 2009»
13 years 5 months ago
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
TVLSI
2008
116views more  TVLSI 2008»
13 years 7 months ago
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
Thermal management is critical for integrated circuit (IC) design. With each new IC technology generation, feature sizes decrease, while operating speeds and package densities incr...
Philip Y. Paik, Vamsee K. Pamula, Krishnendu Chakr...
DAM
2007
100views more  DAM 2007»
13 years 7 months ago
Memory management optimization problems for integrated circuit simulators
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to ...
Timothée Bossart, Alix Munier Kordon, Franc...
CDES
2006
149views Hardware» more  CDES 2006»
13 years 8 months ago
Crosstalk at the Dynamic Node of Domino CMOS Circuits
- The need for faster circuits in smaller area with lower power dissipation has made it a common practice to use the domino CMOS in high performance integrated circuits. However th...
Waleed Al-Assadi, Vipin Sharma, Pavankumar Chandra...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
13 years 11 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
EVOW
2001
Springer
13 years 12 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
SBCCI
2009
ACM
131views VLSI» more  SBCCI 2009»
14 years 3 days ago
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and...
Hagen Sämrow, Claas Cornelius, Frank Sill, An...
ISPD
2004
ACM
161views Hardware» more  ISPD 2004»
14 years 26 days ago
Early-stage power grid analysis for uncertain working modes
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar