Low-Latency Asynchronous FIFO's Using Token Rings

This paper presents several new asynchronous FIFO designs. While most existing FIFO’s trade higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once they are enqueued. Each cell’s input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Two novel protocols are introduced with various degrees of parallelism, as well as four different implementations. The

• Type: Conference
• Year: 2000
• Where: ASYNC
• Authors: Tiberiu Chelcea, Steven M. Nowick
• Keywords: ASYNC 2000, Asynchronous Fifo Designs, Common Data Buses, FIFO’s Trade, Hardware