A sensitivity based placer for standard cells

We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may not impact the path delay in the same way. For each net in the design, we compute the net sensitivity, or the path delay reduction as a result of net length improvements. We use very accurate delay models that include the impact of waveform slope and driver loading effects. Our new timing driven algorithm uses the sensitivity information to focus on nets that have the greatest impact on improving the worst circuit paths. Our method significantly improves the worst path delay over existing published work on industry circuits.

• Type: Conference
• Year: 2000
• Where: GLVLSI
• Authors: Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
• Keywords: GLVLSI 2000, Net Length, Path Delay, Path Delay Reduction, VLSI