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» A sensitivity based placer for standard cells
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GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
14 years 3 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 7 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
14 years 5 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ISPD
2005
ACM
221views Hardware» more  ISPD 2005»
14 years 4 months ago
Kraftwerk: a versatile placement approach
During the ispd05 placement contest, we employed the forcedirected approach Kraftwerk for global placement complemented by the network-flow based final placer Domino. These powe...
Bernd Obermeier, Hans Ranke, Frank M. Johannes
TCAD
2008
99views more  TCAD 2008»
13 years 10 months ago
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few...