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ICCD
2000
IEEE

Power-Sensitive Multithreaded Architecture

14 years 4 months ago
Power-Sensitive Multithreaded Architecture
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for singlethread architectures.
John S. Seng, Dean M. Tullsen, George Cai
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where ICCD
Authors John S. Seng, Dean M. Tullsen, George Cai
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