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ITC
2000
IEEE

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Using on-chip test pattern compression for full scan SoC designs

14 years 3 months ago

Using on-chip test pattern compression for full scan SoC designs

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Helmut Lang, Jens Pfeiffer, Jeff Maguire

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Hardware | ITC 2000 |

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Added	31 Jul 2010
Updated	31 Jul 2010
Type	Conference
Year	2000
Where	ITC
Authors	Helmut Lang, Jens Pfeiffer, Jeff Maguire

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