Timing Analysis with Implicitly Specified False Paths

We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each node one has to store the number of delays which is proportional to that of false paths going through the node. We propose a reduction technique that allows one to drastically reduce the number of delays to store. In particular, the technique can be applied when false paths are implicitly specified by a set of through-path exceptions or false sub-graphs. In addition, we introduce a new data e for representing false paths called abstract false graphs which are as expressive as false subgraphs but are as compact as through-path exceptions. A preliminary prototype implementation illustrates the potential benefits of our reduction technique by showing up to exponential reduction in memory usage and run-time over previous work.

• Type: Conference
• Year: 2000
• Where: VLSID
• Authors: Eugene Goldberg, Alexander Saldanha
• Keywords: False Paths, Reduction Technique, Through-path Exceptions, VLSI, VLSID 2000