Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has been constructed. It has been shown that this space is in nite, and contains the currently established functional fault models. New fault models in this space have been identi ed and veried using resistive and capacitive defect inje ction and simulation of a DRAM model.
A. J. van de Goor, Zaid Al-Ars