Gate-level aged timing simulation methodology for hot-carrier reliability assurance

- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a unique algorithm. The ratio based model simplifies the aging I-V characteristics of MOSFET over time into the aged timing and the corresponding ratio at gate-level. A new algorithm is proposed including a gate primitive decomposition method and an aged slew rate propagation method. This algorithm provides good stress representation and can achieve comparable accuracy with the conventional transistor-level approach. The above methodology has been implemented in a new simulator. Experimental results demonstrate that the simulator based on this methodology realizes full-chip circuit capacity and can be applied to various reliability analyses including degradation-sensitive critical paths and clock skew.

• Type: Conference
• Year: 2000
• Where: ASPDAC
• Authors: Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
• Keywords: ASPDAC 2000, Hardware, Hot-carrier Reliability Assurance, Methodology, Timing Simulation Methodology