Analytical minimization of half-perimeter wirelength

Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelength HPWL of hyperedges in the original circuit hypergraph provided timing constraints are met. Analytical placers are instrumental in handling non-linear timing models 9, 3 , but have two important drawbacks: a corresponding optimization algorithms are typically slower than top-down methods driven by multi-level mincut partitioning 2 , and b hyperedges must be represented with net models 10, 17, 15, 8, 21, 20 which imply a mismatch of objective functions, with the alternative of computationally expensive linear programming LP 25, 16 . By comparing to optimal solutions produced by linear programming, we show that net models lead to solution quality loss. To address this problem, we present the rst analytical algorithm that does not require net models and permits a direct inclusion of non-linear delay t...

• Type: Conference
• Year: 2000
• Where: ASPDAC
• Authors: Andrew A. Kennings, Igor L. Markov
• Keywords: ASPDAC 2000, Hardware, Linear Programming, Net Models, Non-linear Timing Models