New clock-gating techniques for low-power flip-flops

Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application. Keywords CMOS digital integrated circuits, flip-fops, low-power circuits, transition probability.

• Type: Conference
• Year: 2000
• Where: ISLPED
• Authors: Antonio G. M. Strollo, E. Napoli, Davide De Caro
• Keywords: Hardware, ISLPED 2000, Low Power Flip-flops, Power Dissipation, Sensible Power Dissipation