A framework for testing core-based systems-on-a-chip

Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions. In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs. First, we develop a common ground for addressing issues such as core test requirements, core access and test hardware additions. For this purpose, we introduce finite-state automata for modeling tests, transparency modes and test hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data which can again be modeled using finite-state automata. While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automaton, this work extends the methodology to the system level, and, additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time....

• Type: Conference
• Year: 1999
• Where: ICCAD
• Authors: Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
• Keywords: Compact Test Solutions, Hardware, ICCAD 1999, Low-overhead Compact Test, Test Hardware