ActiveOS: Virtualizing Intelligent Memory

Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Such architectures o er a potential solution to the growing communication bottleneck between conventional microprocessors and memory. Previous studies, however, have focused upon single-chip systems and have largely neglected o -chip communication in larger systems. We introduce ActiveOS, an operating system which demonstrates multi-process execution on Active Pages OCS98], a page-based intelligent memory architecture. We present results from multiprogrammed workloads running on a prototype operating system implemented on top of the SimpleScalar processor simulator. Our results indicate that paging and inter-chip communication can be scheduled to achieve high performance for applications that use Active Pages with minimal adverse e ects to applications that only use conventional pages. Overall, ActiveOS allows ...

• Type: Conference
• Year: 1999
• Where: ICCD
• Authors: Mark Oskin, Frederic T. Chong, Timothy Sherwood
• Keywords: Active Pages, DRAM Memory Chip, Hardware, ICCD 1999, Page-based Intelligent Memory