In this paper, we present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most of previous approaches, we app...
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
The architecture of the TriMedia CPU64 is based on the TM1000 DSPCPU. The original VLIW architecture has been extended with the concepts of vector processing and superoperations. ...
Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndho...
High resistance bridges (resistive bridges) are becoming more common. Such bridges cause speed failures. Published experimental results show that current tests are not good at det...
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
With the reducing distances between wires in deep submicron technologies, coupling capacitances are becoming significant as their magnitude becomes comparable to the area capacita...
Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. P...
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...