Speculation Techniques for Improving Load Related Instruction Scheduling

14 years 3 months ago

Download www.cs.binghamton.edu

State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, and resource availability. Most existing instruction schedulers are doing a less than optimal job of scheduling memory accesses and instructions dependent on them, for the following reasons:

Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan

Real-time Traffic