ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...