Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System

This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220µs. We show that for such fast reactive systems, the software overhead of a Real Time Operating System (RTOS) becomes a limiting factor, consuming up to 77% of the total execution performance. We analyze features of different FPGA architectures in order to solve the system performance bottleneck. We show that moving functionality from software to hardware through exploiting the fine grained on-chip SRAM capability of the Xilinx XC4000 architecture, that feature eliminates the RTOS overhead by only a slight increase of about 28% of the used FPGA CLB resources. These investigations have been conducted using our own emulation

• Type: Conference
• Year: 1999
• Where: FPGA
• Authors: Karlheinz Weiß, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel
• Keywords: FPGA, FPGA 1999, Grained On-chip Sram, Real Time Constraints, Real Time Operating System