RT-level TPG Exploiting High-Level Synthesis Information

High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to Genetic Algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.

• Type: Conference
• Year: 1999
• Where: VTS
• Authors: Silvia Chiusano, Fulvio Corno, Paolo Prinetto
• Keywords: Hardware, Pattern Generation Phase, Simulation-based Atpg System, Test Pattern Generation, VTS 1999