Verification by Simulation Comparison using Interface Synthesis

One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the results are usually checked by simulation. In consequence, both the behavioral specification and the HLS results have to be simulated by the same set of test vectors. Due to the HLS and the inherent changes in the cycle-by-cycle behaviour, the synthesis results require an adaption of the initial test vector set. This reduces the advantage gained by using the automated HLS process. In order to decrease these simulation efforts, in this paper a new method will be presented that enables the usage of the same simulation at both abstraction levels and the execution of an automated simulation comparison.

• Type: Conference
• Year: 1998
• Where: DATE
• Authors: Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel
• Keywords: DATE 1998, Hardware, HLS Process, Initial Test Vector, Test Vector